(1) Field of the Invention
This invention relates generally to the field of digital clock circuits and relates more specifically to a clock circuit, which can be instantly suspended and then resumed again with whole width clock pulses.
(2) Description of the Prior Art
Especially in applications as charge pumps or memory cells oscillators are used to provide clock signals. It is often required to suspend and then to resume the operation of such a clock. The challenge of the designers of such circuits is to allow a digital clock signal to be instantly halted without glitches, either in the high or low state, and then resume under control of an asynchronous “suspend” signal.
A glitch is defined as a high/low period that has not the same “width” as an input clock high/low period.
For example, a use for this would be a clock for a charge pump, which has to be instantly “suspended” and then “resumed” with whole width clock pulses.
There are patents or patent publications dealing with clock circuits, which can be suspended and then resumed, but they stop the output clock in a fixed state only (for example always low) after the suspend signal has occurred:
U.S. Patent (U.S. Pat. No. 5,808,486 to Smiley) proposes a clock enabling circuit that generates an output clock signal such that when the enable output signal changes to a logical false, the output clock signal returns to its steady-state value in a manner that does not produce any glitches, and preserves the duty cycle of the input clock. The circuit comprises a first D flip-flop that is positive-edge triggered, a second D flip-flop that is negative-edge triggered, and a two-input AND gate. The first flip-flop has the D input connected to a constant positive voltage, the positive-edge triggered clock input connected to the input clock signal, the Q output connected to the AND gate, and the Q-complement output connected to the asynchronous reset of the second flip-flop. The second flip-flop has the D input connected to the enable output signal, the negative-edge triggered clock input connected to the input clock signal, the Q output connected to the asynchronous reset of the first flip-flop, and the Q-complement output connected to the AND gate. The output of the AND gate is the output clock signal.
U.S. Patent Application Publication (US 2007/0152719 to Wu et al.) discloses a clock switching circuit, which comprises: a clock generator, receiving two different clock signals; a logic gate, coupled to an enable-signal generator and an output-clock generator, wherein during clock switching, the logic gate turns off output clock according to the signal edges of those two clock signals to avoid the problems of clock glitch and timing insufficiency, and the logic gate will not restore clock output until an appropriate timing occurs.
(U.S. Pat. No. 7,295,044 to Bucossi et al.) proposes a digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock signal and a reference voltage, and generates a first output signal. The second differential comparator circuit receives the positive and negative differential clock signal, and generates a second output signal. The third differential comparator circuit receives the reference voltage and the negative differential clock signal, and generates a third output signal. A high-high detecting circuit receives the first output signal, and the third output signal, and generates an Enable signal. The digital clock generation circuit further includes a latch circuit which receives the second output signal, and the Enable signal and generates a digital clock signal. The latch circuit comprises a latch with glitch or noise immunity.
(U.S. Pat. No. 6,021,501 to Shay) discloses a power management system. The system includes an oscillator interface for use in a power management system, a power recycle circuit for use in a power management system, a pad clock and self test for use in a power management system, a clock enable circuit for use in a power management system, a power level detect circuit for use in a power management system, an internal source clock generation circuit for use in a power management system, and a power-save mode change detection circuit for use in a power management system. The oscillator interface includes an circuit for interfacing with an external oscillator used as a source of oscillations. A clock stabilization filter masks out spurious crystal frequencies in the oscillations during start-up of the power management system following an enabling of a feedback loop. The clock stabilization filter has circuitry which provides that the oscillations will start with a rising transition after filtering. A bypassing circuit enables the clock stabilization filter when the external oscillator is a crystal oscillator and for bypassing the clock stabilization filter when the external oscillator is a can oscillator. A masking circuit masks the oscillations from the rest of the power management system. The masking circuit has circuitry which disables the clock masking after a falling edge of the oscillations and stats back up with a rising transition of the oscillations.